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| TLE8242-2 8 channel fixed frequen cy constant current control with current profile detection data sheet, rev. 1.0, feb 2010 automotive power
data sheet 2 rev. 1.0, 2010-02-09 TLE8242-2 table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 direct pwm mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.2 constant current mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 functional description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 supply and reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 input / output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.1 on-state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 off-state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 current feedback registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 direct pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7.1 selecting the frequency of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7.2 selecting the duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8 current profile detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8.1 zone 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8.2 zone 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8.3 zone 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8.4 current profile time out & detection interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.9.2 spi message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.9.2.1 spi message #0 - ic version / manu facturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.9.2.2 spi message #1 - control method and fault mask conf iguration . . . . . . . . . . . . . . . . . . . . . . . . 39 5.9.2.3 spi message #2 - diagnostic configur ation (channel 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.9.2.4 spi message #3 - diagnostic configur ation (channel 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.9.2.5 spi message #4 - diagnostic read (channel 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5.9.2.6 spi message #5 - diagnostic read (channel 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 5.9.2.7 spi message #6 - pwm offset (channel 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.9.2.8 spi message #7 - pwm offset (channel 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.9.2.9 spi message #8 - main period set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.9.2.10 spi message #9 - control variable set (kp and ki) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 5.9.2.11 spi message #10 - current and dither amplitude set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.9.2.12 spi message #11 - dither period set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table of contents data sheet 3 rev. 1.0, 2010-02-09 TLE8242-2 table of contents 5.9.2.13 spi message #12 - max / min current read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.9.2.14 spi message #13 - average curren t read over dither period . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.9.2.15 spi message #14 - autozero trigger / read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.9.2.16 spi message #15 - pwm duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.9.2.17 spi message #16 - current profile detection setup 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.9.2.18 spi message #17 - current profile detection setup 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.9.2.19 spi message #18 - current profile detection feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.9.2.20 spi message #19 - read generic flag bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1 further application informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 pg-lqfp-64 type package marking TLE8242-2 pg-lqfp-64 TLE8242-2l data sheet 4 rev. 1.0, 2010-02-09 8 channel fixed frequency constant current control with current profile detection TLE8242-2 1overview 1.1 features ? low side constant current control pre-driver integrated circuit ? eight independent channels ? output current programmable with 11 bit resolution ? current range = 0 to 1.2a (typ) with a 0.2 ? sense resistor ? resolution = 0.78125 ma/bit (typ) with a 0.2 ? sense resistor ? +/- 2% full scale error over temperature when autozero is used ? programmable pwm frequency via spi from approximately 10 hz to 4 khz (typ) ? programmable kp and ki coefficients for the pi controller for each channel ? programmable superimposed dither ? dither programmed by setting a dither step size a nd the number of pwm periods in each dither period ? programmed via the spi interface ? the dither for each channel can be programmed independently ? programmable synchronization of the pwm control signals ? phase delay time set via the spi interface ? synchronization initiated via si gnal at the phase_sync input pin ? channels within one device and between multiple devices can be synchronized ? each channel can be configured to for constant current control or for direct pwm control via spi ? in direct pwm mode, a current prof ile detection function is engaged ? verifies solenoid armature movement ? profile characteristics programmed via spi ? pass / fail status can be read via spi ? interface and control ? 32 bit spi (serial peripheral interface) - slave only ? enable pin to disable all channels or freeze all channels ? active low reset_b pin resets in ternal registers to their default state and disables all channels ? open drain fault pin can be programmed to transition low when various faults are detected ? 5.0v and 3.3v logic compatible i/o ? protection ? over current shutdown - monitored at posx pin ? programmable over current threshold ? programmable over current delay time ? programmable over current retry time ? battery pin (bat) overvoltage shutdown data sheet 5 rev. 1.0, 2010-02-09 TLE8242-2 overview ? diagnostics ? over current ? open load in on state ? open load in off state ? short to ground ? test complete bit - indicates that fault detection test has completed ? control loop monitor capabilities ? the average current measurement over the last comp leted dither cycle for a selected channel can be accessed via spi ? the minimum and maximum current measurements over the last completed dither cycle for a selected channel can be accessed via spi. this data can be used to measure the achieved dither amplitude ? the duty cycle of each channel can be accessed via spi ? the auto zero values used to cancel the offset s of the input amplifiers can be accessed via spi ? required external components: ? n-channel logic level (5v) mosfet transistor with typical ron 100 m ? (e.g. spd15n06s2l-64) ? recirculation diode (ultrafast) ? sense resistor (0.2 ? for 1.2a average output current range) ? green product (rohs compliant) ? aec qualified 1.2 applications ? variable force solenoids (e.g. automatic transmission solenoids) ? other constant current solenoids ? idle air control ? exhaust gas recirculation ? vapor management valve ? suspension control 1.3 general description the tle8242g ic is an eight channel low-side consta nt current control predriver ic. each channel can be configured to function either in direct pwm mode or in constant current mode by setting the appropriate cm bit in spi message #1. 1.3.1 direct pwm mode operation for direct pwm operation, the posx and negx pins must be co nnected to the circuit in either of the configurations shown in figure 1 . if the sense resistor is included, the load current can be monitored by the microcontroller via a spi command. the open load in on state fault dete ction feature is disabled in direct pwm mode. note: an external flyback clamp is required in th is configuration otherwise the ic may be damaged. TLE8242-2 overview data sheet 6 rev. 1.0, 2010-02-09 figure 1 external circuit diagram for direct pwm mode operation 1.3.2 constant current mode operation during constant current operation, the posx and negx pins must be connected to the circuit in the configuration shown in figure 2 . note: an external recirculation diode is required in this configuration otherwise the ic may be damaged. figure 2 external circuit diagram for constant current mode operation during constant current operation, the pwm control signal driven at the outx pin is controlled by the control loop shown in figure 3 . the pwm frequency is programmed via the spi me ssage # 8. in this message the main period 10nf 0.2 ? pwm or on/off solenoid vs posx negx outx electronic module 10nf 0.2 ? constant current solenoid vs vs posx negx outx electronic module data sheet 7 rev. 1.0, 2010-02-09 TLE8242-2 overview divider, n, can be set to any value between 79 and 2 14 -1 and the divider m can be set to 32, 64, or 128. in direct pwm mode, the value m can also be set to 512. the equation for calculating the pwm frequency is: in constant current mode, the value of m is the number of a/d samples within one pwm period. setting the sam bit in spi message #8 to a ?1? will cause the adc samples i mmediately following a change in the state of the outx pin to be discarded. if the sam bi t is set to ?0?, all m a/d samples are used in the average calculation. the 11 bit current set point is programmed via the spi message #10. the equation for calculating the current setpoint is: the proportional coefficient (kp) and the integral coef ficient (ki) of the control loop are programmed in spi message #9. the kp and ki values should be set to values that result in the desired transient response of the control loop. the duty cycle of the outx pin can be calculated from the difference equations: where error is the differen ce between the commanded average current and measured average current in units of amps. where k indicates the integer number of pwm periods t hat have elapsed since current regulation was initiated. n m f f ? = clk pwm [ohm] r [mv] 320 2 (11bit) setpoint [ma] setpoint current sense 11 ? = () () () ) 1 ( ] [ 1 * ] [ ) ( ) ( ] [ 1 * ] [ ? + ? ? ? ? = + ? ? ? ? = k int a k error n m 0.04 ohm rsense ki k int k int a k error n m 0.04 ohm rsense kp k dutycycle TLE8242-2 overview data sheet 8 rev. 1.0, 2010-02-09 figure 3 control loop - simplified diagram table 1 describes the effect on the integrat or of the pi controller of several events. table 1 control loop integrator control condition action to integrator reset active cleared v5d undervoltage cleared v5ax undervoltage cleared enable pin low (spi message #10 bit en = 0) cleared enable pin low (spi message #10 bit en = 1) remains operational vbat overvoltage held at current value short to bat cleared phase_sync transition remains operational integrator value fo r first pwm cycle = value from end of last complete pwm cycle. average current set to 0 cleared control mode set to direct pwm cleared main period set (n, m) changed remains operational kp, ki settings changed remains operational a/d average autozero value ?on? - current set point dither step size dither generation + + + kp ki pwm block + + dither steps outx posx negx amp + - auto zero autozero value ?off? dut y cycle avg current read italics = can be monitored via spi underlined = can be programmed via spi current readout min current read max current read cl k di rect pwm data sheet 9 rev. 1.0, 2010-02-09 TLE8242-2 overview auto zero the tle8242 includes an autozero featur e for each channel. when the setpoint of a channel is set to 0 ma and the autozero is triggered by an spi co mmand, the offset of the amplifiers and analog to digital converters are measured. the time required for the autozero s equence is calculated ac cording to the formula: the measured offsets can be read via spi message #14. these offsets will be subtracted from the a/d converter output as shown in figure 3 when the current set point is greater than 0. dither a triangular dither waveform can be superimposed on the current set point by setting the amplitude and frequency parameters of the dither waveform via spi messages #10 and #11. see the spi message section for details. the first programmed value is the step size of the dither waveform which is the number of bits added or subtracted from the setpoint per pwm period. one lsb of the dither step size is 1/4 th the magnitude of the nominal setpoint current value. the second programmed value is the number of steps in one quarter of the dither waveform. when dither is enabled, a new average current set poin t will not be activated until the current dither cycle has completed. the dither cycle is comple ted on the positive zero crossing of the dither waveform. a new dither amplitude setting or a new dither frequency setting will also not be activated until the current dither cycle has completed. see figure 4 . figure 4 new dither values programmed and the resulting waveform timing note: the actual measured dither waveform is attenuated and phase shifted according to the frequency response of the control loop. clk az f n m 4 t ? ? = pwm_start dither dither parameter change TLE8242-2 block diagram data sheet 10 rev. 1.0, 2010-02-09 2 block diagram figure 5 block diagram pos0 out0 neg0 sck si so cs_b fault reset_b phase_sync v5d gnd_d gnda1 clk enable v_signal test power pos1 out1 neg1 pos2 out2 neg2 pos3 out3 neg3 pos4 out4 neg4 pos5 out5 neg5 pos6 out6 neg6 pos7 out7 neg7 logic spi interface so supply bat a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile a/d converter pwm d iagnost ics current control, dither, pwm, autozero, c hannel logic, c urrent prof ile v5a1 v5a2 v5a3 gnda2 gnda3 sci3 sco2 sco3 amux gndsa gndsd data sheet 11 rev. 1.0, 2010-02-09 TLE8242-2 pin configuration 3 pin configuration 3.1 pin assignment figure 6 pin configuration 3.2 pin definitions and functions pin symbol function 1neg0 channel #0 negative sense pin; connect to the ?fet? side of the external sense resistor 2pos0 channel #0 positive sense pin; connect to the ?load? side of the external sense resistor 3nc not connected; do not connect to external supply, ground, or signal 4v5a1 supply voltage; 5v input for analog circuits. an external capacitor is to be connected between this pin and gnd_a near this pin 5 (t) sco2 test pin; used for ic test. must be c onnected to gnd_d for specified operation of the ic 6 (t) sco3 test pin; used for ic test. must be c onnected to gnd_d for specified operation of the ic 7gnd_a1 ground; ground pin for analog circuits 8gndsa ground; ground pin for substrate connection near analog circuits 1 17 33 49 tle8242l adler2 64 16 32 48 neg0 pos0 nc v5a1 sco2 sco3 gnda1 gndsa gnda2 amux reset_b v5a2 nc bat pos4 neg4 nc neg1 pos1 nc out0 out1 gnda3 nc v5a3 out2 out3 nc pos2 neg2 neg3 pos3 nc cs_b sck si so v_signal fault gndsd gnd_d clk test phase_sync v5d nc enable nc nc neg5 pos5 nc out4 out5 nc sci3 nc out6 out7 nc pos6 neg6 neg7 pos7 TLE8242-2 pin configuration data sheet 12 rev. 1.0, 2010-02-09 9gnd_a2 ground; ground pin for analog circuits 10 (t) amux test pin; used for ic test. must be c onnected to gnd_d for specified operation of the ic 11 (t) test test pin; used for ic test. must be c onnected to gnd_d for specified operation of the ic 12 v5a2 supply voltage; 5v input for analog. an external capacitor is to be connected between this pin and gnd_a near this pin 13 nc not connected; do not connect to external supply, ground, or signal 14 bat battery sense input; for over-voltage detection. connect through a series resistor (e.g. 1 k ohm) to the solenoid supply voltage. a large electrolytic capacitor (e.g. 47uf) should be placed between the bat supply and ground 15 pos4 channel #4 positive sense pin ; connect to the ?load? side of the external sense resistor 16 neg4 channel #4 negative sense pin ; connect to the ?fet? side of the external sense resistor 17 nc not connected; do not connect to external supply, ground, or signal 18 neg5 channel #5 negative sense pin ; connect to the ?fet? side of the external sense resistor 19 pos5 channel #5 positive sense pin; connect to the ?load? side of the external sense resistor 20 nc not connected; do not connect to external supply, ground, or signal 21 out4 gate driver output for channel #4; connect to the gate of the external mosfet 22 out5 gate driver output for channel #5; connect to the gate of the external mosfet 23 nc not connected; do not connect to external supply, ground, or signal 24 (t) sci3 test pin; used for ic test. must be c onnected to gnd_d for specified operation of the ic 25 nc not connected; do not connect to external supply, ground, or signal 26 out6 gate driver output for channel #6 ; connect to the gate of the external mosfet 27 out7 gate driver output for channel #7; connect to the gate of the external mosfet 28 nc not connected; do not connect to external supply, ground, or signal 29 pos6 channel #6 positive sense pin; connect to the ?load? side of the external sense resistor 30 neg6 channel #6 negative sense pin; connect to the ?fet? side of the external sense resistor 31 neg7 channel #7 negative sense pin ; connect to the ?fet? side of the external sense resistor 32 pos7 channel #7 positive sense pin ; connect to the ?load? side of the external sense resistor 33 nc not connected; do not connect to external supply, ground, or signal pin symbol function data sheet 13 rev. 1.0, 2010-02-09 TLE8242-2 pin configuration 34 enable enable logic input; when this input pin is low all channels are turned off (zero current) or remain in their last state, depending on how the channel is programmed to respond 35 nc not connected; do not connect to external supply, ground, or signal 36 v5d supply voltage; 5v input for digital circuits. an external capacitor is to be connected between this pin and gnd_d near this pin 37 phase_sync phase synchronization input: used to synchronize the rising edges of the pwm signal on the outx pins for each channel 38 reset_b reset input; when this input pin is low all channels are turned off and all internal registers are reset to the default state. the part must be held in reset by an external source until all supp lies are stable and within tolerance 39 clk clock; main clock input for the chip. a cl ock input of 20 mhz to 40 mhz is required 40 gnd_d ground; ground pin for digital circuits 41 gndsd ground; ground pin for substrate connection near digital circuits 42 fault fault output pin; open drain output pin is pulled low when a fault condition is detected. certain faults can be masked via spi 43 v_signal supply voltage; supply pin for the spi so output and the pull-up current sources of the digi tal inputs cs_b and reset_b. an external ca pacitor must be connected between this pin and gnd_d near this pin 44 so spi serial data out 45 si spi serial data in 46 sck spi serial clock input 47 cs_b spi chip select bar; active low signal 48 nc not connected; do not connect to external supply, ground, or signal 49 pos3 channel #3 positive sense pin ; connect to the ?load? side of the external sense resistor 50 neg3 channel #3 negative sense pin ; connect to the ?fet? side of the external sense resistor 51 neg2 channel #2 negative sense pin ; connect to the ?fet? side of the external sense resistor 52 pos2 channel #2 positive sense pin ; connect to the ?load? side of the external sense resistor 53 nc not connected; do not connect to external supply, ground, or signal 54 out3 gate driver output for channel #3 ; connect to the gate of the external mosfet 55 out2 gate driver output for channel #2; connect to the gate of the external mosfet 56 v5a3 supply voltage; 5v input for analog. an external capacitor is to be connected between this pin and gnd_a near this pin. 57 nc not connected; do not connect to external supply, ground, or signal 58 gnd_a3 ground; ground pin for analog circuits 59 out1 gate driver output for channel #1 ; connect to the gate of the external mosfet pin symbol function TLE8242-2 pin configuration data sheet 14 rev. 1.0, 2010-02-09 60 out0 gate driver output for channel #0; connect to the gate of the external mosfet 61 nc not connected; do not connect to external supply, ground, or signal 62 pos1 channel #1 positive sense pin; connect to the ?load? side of the external sense resistor 63 neg1 channel #1 negative sense pin ; connect to the ?fet? side of the external sense resistor 64 nc not connected; do not connect to external supply, ground, or signal pin symbol function data sheet 15 rev. 1.0, 2010-02-09 TLE8242-2 general product characteristics 4 general product characteristics 4.1 maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 battery input (vbat) v bat -13 50 v ? 4.1.2 supply voltage (logic) v 5d, v 5a1 v 5a2, v 5a3 v signal -0.3 6.0 v ? 4.1.3 posx, negx v pos, v neg -0.3 50 v ? 4.1.4 posx-negx v pos- v neg -0.2 13 v ? 4.1.5 outx v out -0.3 min(v 5d + 0.3; 6) v? 4.1.6 reset_b, si, sck, cs_b, clk, test, phase_sync, enable v io -0.3 min(v 5d + 0.3; 6) v? 4.1.7 so, fault v io -0.3 min(v signal + 0.3; 6) v? 4.1.8 maximum difference between v5d and v5ax pins -500 500 mv ? currents 4.1.9 input clamp current enable, phase_sync, reset_b, si, sck, cs_b, clk i clamp 5?5ma 2) 2) current needs to be limited only when maximum voltages are exceeded temperatures 4.1.10 storage temperature t stg -65 150 c? 4.1.11 junction temperature t j -40 150 c? esd susceptibility 4.1.12 hbm -2 2 kv 3) 3) esd susceptibility hbm accord ing to eia/jesd 22-a 114b 4.1.13 cdm all pins -500 500 v 4) 4) esd susceptibility cdm according to eia/jesd22-c101 4.1.14 cdm corner pins -750 750 v 4) TLE8242-2 general product characteristics data sheet 16 rev. 1.0, 2010-02-09 4.2 functional range t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance t j = -40 c to +150 c; all voltages with respect to ground, posit ive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage range for normal operation - vbat v bat 5.5 42 v ? 4.2.2 supply voltage range for normal operation - v5d, v5a1, v5a2, v5a3 v v5d v v5a1 , v v5a2 , v v5a3 4.75 5.25 v ? 4.2.3 supply voltage range for normal operation -v_signal v v_signal 3.0 5.25 v ? 4.2.4 clock frequency f clk 20 40 mhz 4.2.5 pwm frequency for normal operation f pwm 10 4000 hz 4.2.6 extended pwm frequency range f pwm 10 8000 hz parameter deviations possible 4.2.7 common mode voltage range for normal operation - posx, negx pins. v pos , v neg 030v? 4.2.8 extended common mode voltage range for operation - posx, negx pins. v pos , v neg 0 42 v parameter deviations possible pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to ambient 1) 1) not subject to production test, specified by design. r thja ?38?k/w 2) 2) specified r thja value is according to jedec jesd51-2, -7 at nat ural convection on fr4 2s2p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m, 2 x 35 m cu). data sheet 17 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5 functional description and electrical characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 o c and the given supply voltage. 5.1 supply and reference the device includes a power-on reset circuit. this feature will disable t he channels and reset the internal registers to their default values when the voltage on v5a1, v5a2, v5a3, and/or v5d are below their respective reset thresholds. the v5d pin and gnd_d pin are the supply and ground pins for the digital circuit blocks. the current through these pins contain high frequency components. decoupling with ceramic capacitors and careful pcb layout are required to obtain good emc performance. the v5a1, v5a2, v5a3 pins and gnd_a pin are the supp ly and ground pins for the analog circuit blocks. the v_signal pin supplies the spi output pin (so) and is the source voltage for the pull up currents on the cs_b and reset_b pins. v_signal should be connected to the i/o supply of the microc ontroller (3.3v or 5.0v). the bat pin is an input pin used to detect over voltage faults . this pin is not a power supply input. a series resistor should be connected between this pin and the solenoid supply voltage for transient protection. electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin ( unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.1.1 undervoltage reset (internally generated) v5a1 , v5a2, and v5a3 v v5a1 , v v5a2 , v v5a3 3.5 ? 4.5 v internal reset occurs if v5a1 v5a2, or v5a3 is below the undervoltage limit 5.1.2 undervoltage reset (internally generated) v5d v v5d 1.0 ? 4.5 v internal reset occurs if v5d is under the undervoltage limit 5.1.3 v5d supply current i v5d ??75 40 ma ma f clk =40mhz f clk =20mhz 5.1.4 v5a1 supply current i v5a1 ??20ma 5.1.5 v5a2 supply current i v5a2 ??20ma 5.1.6 v5a3 supply current i v5a3 ??5ma 5.1.7 v_signal supply current i v_signal ??300 av signal =5.25v so = hi-z state 5.1.8 vbat current i vbat ??80 a full operating range 5.1.9 vbat curren t - unpowered i vbat ??5 a v5d=v5ax=0v, bat=14v TLE8242-2 functional description and electrical characteristics data sheet 18 rev. 1.0, 2010-02-09 5.2 input / output all digital inputs are compatib le with 3.3 v and 5 v i/o logic levels. the su pply voltage for the spi output so is the v_signal pin. all digital inputs are pulled to a known stat e by a weak internal current source or current sink when not connected. however, unused digital input pins should be connected to ground or to v_signal (according to the desired functionality) by an exte rnal connection or resistor. all input pin weak internal current sources are supplied by the v_signal pin. the reset_b pin is an active low input pi n. when this pin is low, all channels are off, and all internal registers are reset to their default states. the device must be held in reset by an external source until all the power supplies have stabilized. the ic contains an in ternal power on and und ervoltage reset which be comes active when v5d, v5a1, v5a2, or v5a3 fall below th e undervoltage reset thresholds. the enable pin is an active high input pin which must be held high for normal operation of the device. when this pin is held low all channels are either turned off or will remain in the la st state, dependi ng on how the enable behavior of the channel is programmed via spi message #10. the default condition is that all channels are turned off when the enable pin is low. the clk pin is the main clock input for the device. the in put thresholds are compatible with 3.3 v and 5.0 v logic levels. no synchronization is required between the clock signal connec ted to the clk pin and the spi clock signal (sck). all internal clock signals of the tle8242 (pwm signals, a/d sampling, diagnostics, etc.) are generated from the this clock input. also, this clock is required for the device to accept and respond to spi messages. figure 7 clk timing diagram the phase_sync pin is an input pin that can be used by the microcontroller to synchronize the pwm control signals of multiple channels. the desired phase delay be tween the rising edge of the signal applied to the phase_sync pin and the rising edge of the pwm signal of each channel can be programmed independently via spi message #6. the equation for calculating the offset is: each time a pulse is received on the phase_sync pin, the ic will latch a bit which is reported via the response to spi message #19. (see spi interface section for bit/me ssage location.) this latch is cleared when the message is read. note: the pwm periods are restarted when a rising edge is detected on the phase_sync pin. a periodic pulse train on this pin will distur b the current regulation. note: after exiting the reset state, a pulse is needed on th e phase_sync pin in order to synchronize the pwm periods of the channels clk t 14 1/f clk t 15 vih min vil max pwm offset f * 32 offset phasesynch t = data sheet 19 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics figure 8 phase synchronization diagram the test, sci3, sco2, sco3, and amux pins are used du ring ic level test. these pins should be connected directly to ground for normal device operation. the fault pin is an open drain output pin. this pin will be pulled lo w by the device when an unmasked fault has been detected. the fault masks are programmed via spi message #1. electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin ( unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.2.1 logic input low voltage v ilmax ??0.8v 5.2.2 logic input high voltage v ihmin 2.0 ? ? v 5.2.3 logic output low voltage v olmax ??0.2v i l =200 a 5.2.4 logic output high voltage v ohmin 0.8*v_ signal ??v i l =-200 a 5.2.5 pull down digital input (si, clk, sck, phase_sync, enable) i pd 10 ? 50 a v in =v_signal 5.2.6 pull up digital input (cs_b, reset_b) i pu -50 ? -10 a v in =0v (current drain from v_signal) 5.2.7 fault pin voltage v fault.low ? ? 0.4 v active state; i fault =2ma 5.2.8 fault pin current i fault,max 2.0 ? ma active state; v fault =0.4v 5.2.9 clk high time (rise 2.0v to fall 2.0v) t 14 8??ns 5.2.10 clk low time (fall 0.8v to rise 0.8v) t 15 8??ns outx pwm/32 clk phase_sync t1 t1 gate turns off on-time cut sh o rt normal turn off time programmed delay = 8/32 pwm periods TLE8242-2 functional description and electrical characteristics data sheet 20 rev. 1.0, 2010-02-09 5.3 diagnostics the tle8242 includes both on-state and off-state diagnosti cs. on-state diagnostics are active when the outx pin is driven high and off-state diagnostics are active when the outx pin is driven low. a detected fault can be used to activate the open drain fault pin on the ic. this pin can be used to interrupt the microcontroller when a fault is detected. certain faults ca n be prevented from activating the fault pin by setting the fault mask register in spi message #1. once a fault is detected it is latched into the respective fault register. the microcontroller can access the fault registers by spi messages #4, #5, and #19. if the reset_b line transitions high-to-low, a rb_l bit is la tched into the gene ric flag bits register. this register is cleared after it is read from the spi, and the rb_l bit will not be set again until the next high-to-low transition occurs on the reset_b pin. if the enable pin voltage is low, the en_l bit is latched in the generic flag bits regi ster. the enl bit is cleared when the enable pin returns to a high state and the g eneric flag bits register is accessed by spi message #19. the diagnostic delay timers for the on-state and off-stat e diagnostic functions are derived from the master clock signal applied to the pin clk using a programmable pr edivider. this predivider is programmable by the diag_tmr bits in spi message #1. three unique fault types are detec ted using 4 different fault bits the fault bit is set to a ?1? if the fault is detected. note: in order to differentiate between a short to ground failure and an open load failure, the channel must be turned off (setpoint = 0ma). tested diagnostic bits table 2 timebase for diagnostics diag_tmr1 diag_tmr0 pre-divider nfault min ... max tested timer and fault detection timer period. f clk =20 mhz f clk =40 mhz 0 0 128 10 ... 11 64 sec 32 sec 0 1 192 10 ... 11 96 sec 48 sec 1 0 128 2 ... 3 12.8 sec 6.4 sec 1 1 256 10 ... 11 128 sec 64 sec table 3 diagnostic flags / bits fault type abr. gate is on gate is off short to ground fault sg ol-on-f reported (=0 in on/off mode) bit sg-f short to battery fault sb bit sb-f open load fault ol bit ol-on-f (=0 in on/off mode) bit ol-off-f clk fault d diag_perio f predivider * n t = data sheet 21 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics the tested bits allow the distinction between a a case when a fault bit is not set because the fault is not detected, and the case when a fault bit is not set because the diagno stic test has not completed. for instance, the calculated duty cycle is too low to comple te the short to battery test. two fault tested bits are defined: the tested bit is set to 1 when the fault test has completed successfully. each fault type can be described by the two bits: fault and tested. table 4 diagnostics tested bits / flags tested type outx high outx low short to ground and open load off tested bit off-t short to battery tested bit sb-t table 5 fault vs. tested bits matrix and interpretation fault tested interpretation by microcontroller 0 0 this fault type has not been tested 0 1 no fault - the fault type has been tested and no fault is present 1 0 this combination cannot occur 1 1 fault - this particular fault type has occurred TLE8242-2 functional description and electrical characteristics data sheet 22 rev. 1.0, 2010-02-09 figure 9 diagnostic block diagram 5.3.1 on-state diagnostics when the outx pin transitions high, the fault timers are cleared to 0 and the te sted timer starts. if the tested timer expires, the bit sb-t (in the spi registers #4 and #5) is se t to 1. if the outx pin transitions low, the tested timer is cleared and then used for the off-state diagnostics. if the analog sb fault signal (sb-fa) changes to 1, the fault filter timer starts. if the fa ult filter timer expires, the digitally filtered sb fault signal (sb-fd) is set to one. if sb-fa changes to 0, sb-fd changes immediately to 0 and the filter timer is cleared to 0. a sb-fd=1 and sb-t=1 switches off the outx signal and t he sb-f bit in the fault regi ster will be set. the outx pin remains in the off state until the fault retry pwm period counter expires. if the spi message #3 or #4 is read, then the sb-f bit and the sb-ft bit in this register are cleared. also, the tested timer is cleared to 0. the short to battery (sb) detection functions in both di rect pwm and constant current mode. the sg-fd and ol- off-fd signals are held to 0 while the outx pin is high. if the tle8242 ic is in direct pwm mode, open load on detection is disabled (ol-on-f = 0). if the tle8242 ic is not in direct pwm mode and the ou tx pin is high for 64 pwm periods, then the open load fault on mode fault is detect ed, and the ol-on-f bit in th e diagnostic register is se t. this bit will be cleared when spi message #3 or #4 is read. if the outx pin remains in a high state, then the open load - on fault condition is detected again after another 64 pwm cycles. predivider 1:128 1:192 1:256 tested timer 1..10 (shared) digital filter open load off (only while off) digital filter short to ground (only while off) digital filter short to battery (only while on) gate on counter 1..64 fault filter timer (1..10) (shared) v pos v ol v pos v sg v pos v sb ol-fa sg-fa sb-fa pwm mode enabled pwm start clear logic divider select (spi register) masterclock ol-off-fd sg-fd sb-fd ol-on-f ol-off-f (open load off fault) sg-f (short to ground fault) sb-f (short to battery fault) ol-on-f (open load on fault) off-t (short to ground and open load off tested) sb-t (short to battery tested) read spi fault register gate is on clear clear clear data sheet 23 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics figure 10 on-state diagnostic timing - short to vbat pwm_start outx vpos load current sb-t sb-f diagnostic read via spi tested timer fault filter fault retry time short to vbat load ok short vsb fault filter tested timer TLE8242-2 functional description and electrical characteristics data sheet 24 rev. 1.0, 2010-02-09 figure 11 open - on 5.3.2 off-state diagnostics the off-state diagnostics function in both c onstant current mode and in direct pwm mode. when the outx pin transitions low, the fault timers are clea red to 0 and the tested timer starts to count up. if the tested timer expires, the bit off-t in th e diagnostic register is set. if a spi diagnostic register read occurs, the tested timer is cleared to 0 and starts again to count up. if the outx pin transitions high, the tested-timer is cleared to zero and then used for on-state diagnostics. if the analog ol fault signal (ol-fa) changes to 1, the fault filter timer starts to count up. if the fault filter timer expires, the digitally filtered ol faul t signal (ol-on-fd) is set to one. if ol-fa changes to 0, ol-fd changes immediately to 0 and the fault filter timer is cleared to 0. if the analog sg fault signal (sg-fa) changes to 1, the faul t filter timer is cleared to 0 and starts to count up. if the fault filter timer expires, the digitally filtered sg fault signal (sg-fd) is set to one. if sg-fa changes to 0, sg-fd changes immediately to 0 and the fault filter timer is cleared to 0. if sg-fd = 1 and the tested timer is expired then the sg-f bit in the fault register is set and the ol-off-f bit in the fault register remains unchanged (independently from ol-off-fd). if sg-fd = 0 and ol-off-fd = 1 then the ol-f bit in the fault register is set. if a spi fault read occurs, the off-t bit, the sg-f bit an d the ol-f bit in the spi registers are cleared to zero (and the timers are cleared to 0). pwm_start outx vpos ol-on-f spi diagnostic read 64 * pwm period data sheet 25 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics figure 12 off-state diagnostics figure 13 off-state diagnostics timing diagram - open negx outx posx v su ppl y sol enoid v5a (vol+vsg)/2 (2.5v) + - - + vol (3v) vsg (1.7v) + oa cmp cmp - digital filter digital filter ol-fa ol-off-fd sg-fa sg-fd tested timer (off) ol-off- fault sg- fault ipu(sg) (150ua) ipd(ol) (150ua) latch latch latch sg/ol-off tested cneg cpos vpos outx off-t ol-off-f spi diagnostic read tested timer fault filter tested timer fault filter load ok open vol vsg TLE8242-2 functional description and electrical characteristics data sheet 26 rev. 1.0, 2010-02-09 figure 14 off-state diagnostics ti ming diagram - short to ground over voltage shutdown and diagnostics if the voltage at the bat pin is above vbat ov , the output drivers set all outx pins to low, and a diagnostic bit is set (spi message #19 bit ov). during over voltage condition the integrator of the stea dy state current control is halted (actual value of the duty cycle is not changed during over voltage). all other func tions operate normally (e.g. adc, dithering, auto zero, filters, ?). electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.3.1 over voltage shutdown v batov 42 ? ? v rising voltage on bat 5.3.2 open load detection voltage v pos(ol) v5a-2.5 ? v5a-1.5 v 5.3.3 pos pin ol pull down current i pd(ol) 90 150 225 av5a=5v, v pos =v neg =v5a 5.3.4 short to gnd detection voltage v pos(shg) v5a-3.8 ? v5a-2.8 v 5.3.5 pos pin sg pull-up current i pu(shg) -280 -150 -90 av5a=5v, v pos =v neg =0v 5.3.6 neg bias current - low common mode i neg(l) -40 ? 10 av5a=5v, v pos =v neg =0v 5.3.7 neg bias current - high common mode i neg(h) 0?60 av5a=5v, v pos =v neg =v5a vpos outx off-t sg-f spi diagnostic read tested timer fault filter tested timer fault filter load ok short to ground vol vsg data sheet 27 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.3.8 pos fault threshold voltage v flt 0.6 0.7 0.8 v pos voltage required to trigger a short to battery fault: config bits = 00 5.3.9 pos fault threshold voltage v flt 0.8 0.9 1.0 v pos voltage required to trigger a short to battery fault: config bits = 01 5.3.10 pos fault threshold voltage v flt 1.0 1.1 1.2 v pos voltage required to trigger a short to battery fault: config bits = 10 5.3.11 pos fault threshold voltage v flt 1.2 1.3 1.4 v pos voltage required to trigger a short to battery fault: config bits = 11 5.3.12 fault filter timer n fault 10 11 clock cycles diag_tmr = 00, 01 and 11 5.3.13 fault filter timer n fault 23clock cycles diag_tmr = 10 5.3.14 fault filter time t ff clock divider (spi message 7) 00, 10- predivider 128 01 - predivider 192 11 - predivider 256 5.3.15 tested timer time t tt clock divider (spi message 7) 00, 10 - predivider 128 01 - predivider 192 11 - predivider 256 v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin ( unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. clk fault f predivider n ? ? TLE8242-2 functional description and electrical characteristics data sheet 28 rev. 1.0, 2010-02-09 5.4 output driver the outx pins of the device are connected to the gates of the external mosfet transistors. the outx pin driver circuits charge and discharge the mosfet gate capacitanc e with a constant current source and sink. the supply for the current source is the v5d pin. in ternal resistors to ground are included on the outx pins so that the external mosfet is held in the off state when power is not applied to the device. an external resistor is typically placed between the outx pin and the gate of the external mosfet in order to set the mosfet turn-on and turn-off times. the value of the re sistor must be chosen such that the turn-on and turn- off times of the mosfet are no longer than 1/(fpwm*32). electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) 5.5 current control electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limi t values unit conditions min. typ. max. 5.4.1 passive gate pull down resistance r pd 50 ? 200 k ? internal pull down resistor present at each outx pin 5.4.2 outx source current i o_src -30 ? -15 ma v out = v5d-2v 5.4.3 outx sink current i o_snk 15 ? 30 ma v out = 2v pos. parameter symbol limi t values unit conditions min. typ. max. 5.5.1 offset error output from average block in figure 3 . 1 count = 320/rsense * 2 -13 ma 0 ? 120 counts autozero disabled.vpos- vneg=0mv vpos, vneg 30v dither disabled 5.5.2 gain error -2 ? 2 % autozero enabled.vpos- vneg=300mv vpos, vneg 30v data sheet 29 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.6 current feedback registers the average current over each pwm cycle is measured re sulting in a 13 bit value. the summation of the 13 bit values for all pwm periods in a dither period can be read by accessing spi message #13. also, the 11 msb?s of the minimum and maximum 13 bit values within a dith er period can be read by accessing spi message #12. average current over dither period when the spi message #13 is read or written, the 13 bi t average current value for each pwm cycle within the dither period is summed beginning with the positive going zero crossing of the dither waveform. the resulting 20 bit value represents the average current over the dither cycle as shown in equation: if dither is disabled (dither steps = 0 or dither amplitude = 0), then th e average current feedback value will be updated every pwm period a nd will be the same as the 13 bit current f eedback value used in the pi controller. the spi message #13 includes a valid bit that indi cates whether the average current measurement has completed since the last register access. when the register is accessed, the valid bit is cleared. the valid bit is set again when the summation is completed and new data has been stored in the register. the summation process runs continuously on the last sele cted channel. so if the same channel is repeatedly selected, new data is always available within one di ther period after the spi register is accessed. if the selected channel is different than the previously selected channel, the summation process does not begin until the beginning of the next dither period. so, ne w data may not be available until two dither cycles have completed. the channel selection for the average dither current feedback message message will also select the channel for the minimum and maximum current over dither period function. minimum and maximum current over dither period when the spi message #12 is read or written, the 13 bi t average current value for each pwm cycle within the dither period is monitored beginning with the positive going zero crossing of the dither waveform. the most significant 11 bits of the minimum and the maximum average current values are stored. if dither is disabled (dither steps = 0 or dither amplitude = 0), then the minimum and maximum values will be updated every pwm pe riod and will be the 11 msb?s of the 13 bit cu rrent feedback value us ed in the pi controller. the spi message #12 includes a valid bit that indicates whether a dither period has completed since the last register access. when the register is accessed, the valid bit is cleared. the valid bit is set again when the dither period is completed and new data has been stored in the minimum and maximum registers. the minimum and maximum detection process runs continuo usly on the last selected channel. so, if the same channel is repeatedly selected, new data is always av ailable within one dither period after the spi register is accessed. if the selected channel is different th an the previously selected channel, the detection process does not begin until the beginning of the next dither period. so, new data ma y not be available until two dither cycles have completed. the channel selection for the minimum and maximum curr ent over dither period me ssage will also select the channel for the average dither current feedback function. [] [ohm] rsense [mv] 320 steps dither 2 current dither avg ma feedback current dither 15 ? ? = TLE8242-2 functional description and electrical characteristics data sheet 30 rev. 1.0, 2010-02-09 5.7 direct pwm control in direct pwm control mode, the pi control loop is disabled. the integrator in the constant current control logic is cleared and held at 0 while direct pwm mode is active. the frequency and duty cycle of the outx pin signal is directly controlled via spi messages. 5.7.1 selecting the fre quency of operation the period of the pwm is programmed in whole numbers of clocks from the clk input (as in constant current mode). the following formula is applied: or the value n is the divider pr ogrammed via the spi interface. the ic will automatically limit the lower value of n to 79. if a value lower than 79 is programmed, the ic shall default n for that channel to 79 and return a value of 79 in the spi response. the maximum value of n is 2 14 -1 as it is programmed as a 14-bit number via spi. if a new value of n is programmed du ring operation, the new value of n will be returned on the next spi message, and the new value of n will be used at the beginning of the next pwm cycl e. the default va lue for n is 625. the value of m is the number of a/d samples in one pwm period. m is programmed with the value 32, 64, 128, or 512 via an spi message. the default value for m is 32. the pwm frequency multiplied by the value m is the analog to digital converter samp le rate. this sample rate must be no greater than 128 khz. 5.7.2 selecting the duty cycle the duty cycle of the pwm is also programmed in whole numb ers of clocks from the clk input. the following formula is applied: pwm duty cycle is a 19 bit value programmed in spi message # 15 ?pwm duty cycle?. or the maximum duty cycle is clipped to 100% n * m * t t clk pwm = = 32 m cycle duty pwm * t t clk on ? = [] 100% n 32 cycle duty pwm % cycle duty ? ? = data sheet 31 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.8 current profile detection the tle8242 will detect curr ent profiles due to the ch ange in inductance caused by the opening/closing of solenoid valves. examples of the types of waveforms seen in this instance are shown in figure 15 and figure 16 . examples of waveforms that fail the current profile detection test are shown in figure 17 and figure 18 . figure 15 current profile diagram - waveform showing valve movement figure 16 current profile diagram - waveform show ing valve movement with non-zero threshold in zone 2 measured current (differential voltage ) a/d samples zone 1 zone 3 timeout for failure pass time out detect interrupt outx voltage zone 2 time out timer a/d samples timeout for failure pass time out detect interrupt outx voltage time out timer measured current (differential voltage ) 3 zone zone zone 2 1 TLE8242-2 functional description and electrical characteristics data sheet 32 rev. 1.0, 2010-02-09 figure 17 current profile diagram - time out failure figure 18 current profile diagram - detection interrupted failure the current profile detection feature is active only in direct pwm mode. the method employed is to look for three specific "patterns" of the current in 3 zones. this detect ion method is generally used for on/off valves. the on/off control of the valve is achieved by selecting the pwm peri od desired and setting to a 0% or 100% duty cycle via spi, however the detection may work wit hin a single pwm on-time with a duty cycle less than 100% if the profile completes before the gate turns off. the pwm period (n and m values) are critical as these va lues set the a/d sample rate used in the current profile detection. the full 10-bit re sult of the a/d converter is used for the cpd function. using a 200 mohm sense resistor, this translates into a resolution of 1.56 ma. measured current (differential voltage ) a/d samples zone 1 timeout for failure pass time out detect interrupt outx voltage zone 2 time out timer measured current (differential voltage ) a/d samples zone 1 timeout for failure pass time out detect interrupt outx voltage zone 2 time out timer data sheet 33 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.8.1 zone 1 when the outx pin transitions from low-to-high, zone 1 of the logic is entered. the tle8242 compares the difference between successive a/d samples and calculat es the addiff value. this value is compared with threshold1 as follows: ? addiff = a/d m+1 - a/d m ? if (addiff > threshold1) then count = count +1 when addiff is greater than threshold 1 for count1 out of count1 + 1 successive comparisons, zone 1 is passed and zone 2 is entered. note that if one of the tests fails, the actual test performed on the next sample after the single failure is ? addiff = a/d m+1 - a/d m-1 ? if (addiff > 2 * threshold1) then count = count +1 this has the effect of filtering out a si ngle noise spike in the a/d measurement. 5.8.2 zone 2 in zone 2, the tle8242 compares the difference be tween successive a/d samples and calculates the addiff value. this value is compar ed with threshold2 as follows: ? addiff = a/d m+1 - a/d m ? if (addiff TLE8242-2 functional description and electrical characteristics data sheet 34 rev. 1.0, 2010-02-09 5.8.4 current profile time out & detection interrupted if the current profile time out value is achieved before th e completion of the test, the current profile test has failed. if this failure occurred, th e current profile time out bit in the spi message is set. the current profile time out value is programmable and should be set to a value less than the pwm period. if the outx pin is turned off before the completion of the test as in figure 18 , the detection interrupted spi bit is set. note that the outx pin must transition from high to lo w to set the detection interrup ted fault bit. the detection interrupted fault bit is not set by the expiration of the pwm period if the duty cycle is set to >= 100%. if the entire cpd test passes (all three zones are pass ed before the time out), the "passed since last read" spi bit is set spi message # 18. each channel of the adler 2 is individually conf igurable for the current profile detection patterns. the thresholds and counts for each zone must not be changed via spi while a current profile detection sequence is active, otherwise an incorrect detection may occur. data sheet 35 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9 serial peripheral interface (spi) spi messages for the tle8242 ic are 32-bit va lues broken down into the following fields. bit 31: read/write bit - 0 = read 1 = write bits 30-24: message identifier bits 23-0: message data in cases where multiple channels re quire the same message structure, bi ts 24-25 of the message identifier represent the channel numbers. the structure follows the following pattern bit 31: read/write bit - 0 = read / 1 = write bits 30-27: message identifier bits 26-24: channel number bits 23-0: message data the message from the microcontroller must be sent msb fi rst. the data from the so pin is sent msb first. the tle8242 will sample data from the si pin on the rising edge of sck and will shift data out of the so pin on the rising edge of sck. all spi messages must be exactly 32-bits long, otherwis e the spi message is discarded. the response to an invalid message (returned in the next spi message) is the message with identifier 00000 (manufacturer id). when the enable pin is low, all spi writes commands are executed as read commands. when reset_b pin is low, the spi po rt is disabled. no spi messages are received and no responses are sent. the so pin remains in a high impedance state. there is a one message delay in t he response to each message (i.e. th e response for message n will be returned during message n+1). read/write operation is referenced from the spi master. the tle8242 ic is the slave device. when bit 31 is = 0 to denote a read operation to the ic, the message data in bits 23-0 of the sent message are ignored, but will contain valid da ta in the response message. all response data (either from a read or write operation) is the direct contents of the addressed internal register, and is not an echo of the data sent in the previous spi message. the response to the first spi message after a reset is message #0 (ic version / manufacturer). TLE8242-2 functional description and electrical characteristics data sheet 36 rev. 1.0, 2010-02-09 5.9.1 spi signal description electrical characteristics: v5d = 4.75v to 5.25v, vbat = 5.5v to 42v, t j = -40 c to +150 c, all voltages with resp ect to ground, positive current flowing into pin (unless otherwise specified) . maximum capacitive load on the so pin = 200 pf. pos. parameter symbol limi t values unit conditions min. typ. max. 5.9.1 lead time t 1 140 ? ? ns cs_b falling (0.8v) to sck rising (0.8v) 5.9.2 lag time t 2 50 ? ? ns sck falling (0.8v) to cs_b rising (0.8v) 5.9.3 dead time t 3 450 ? ? ns cs_b rise (2.0v) to cs_b fall (2.0v) 5.9.4 1/f sck period of sck t 4 100 ? ? ns sck rise to rise 5.9.5 sck to csb set up time t 5 10 ? ? ns sck falling (0.8v) to cs_b fall (2.0v) 5.9.6 sck high time t 6 40 ? ? ns sck high time (rise 2.0v to fall 2.0v) 5.9.7 sck low time t 7 40 ? ? ns sck low time (fall 0.8v to rise 0.8v) 5.9.8 csb to sck hold time t 8 10 ? ? ns cs_b rise (2.0v) to sck rise (0.8v) 5.9.9 si setup time t 9 20 ? ? ns si setup time to sck rise (0.8v) 5.9.10 si hold time t 10 20 ? ? ns si hold time after sck rise (2.0v) 5.9.11 so enable t 11 ? ? 110 ns cs_b fall (2.0v) to so bit0 valid 5.9.12 so valid time t 12 ? ? 80 ns so data valid after sck rise (2.0v) 5.9.13 so disable time t 13 ? ? 110 ns so tristate after cs_b rise (2.0v) 5.9.14 number of clock pulses while cs_b low 32 ? 32 cycles 5.9.15 so rise time t so_rise ? ? 50 ns (20% to 80%) 5.9.16 so fall time t so_fall ? ? 50 ns (80% to 20%) 5.9.17 input pin capacitance. cs_b, si, and sck c in ??20pf 5.9.18 so pin capacitance c so ??25pftristate data sheet 37 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics figure 19 spi timing diagram bit 3 1 msb bit 0 lsb don?t care don?t care clock 1 clock 2 clock 3 clock 31 clock 32 bit 3 0 bit 2 9 bit 1 don?t care bit 0 lsb bit 3 1 msb bit 3 0 high impedance high impedance time time time time don?t care bit 1 don?t care bit 2 9 sck si so t 6 t 4 t 7 t 1 t 5 t 10 t 9 t 11 t 12 t 2 t 3 t 8 t 13 cs _b TLE8242-2 functional description and electrical characteristics data sheet 38 rev. 1.0, 2010-02-09 5.9.2 spi message structure 5.9.2.1 spi message #0 - ic version / manufacturer sent values: ic version / manufacturer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id not used 0000000 1514131211109876543210 not used field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0000 = ic version / manufacturer response: ic version / manufacturer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0msg_id ic manuf id 1514131211109876543210 version number 00000000 field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0000 = ic version / manufacturer ic manuf id 23:16 data ic manufacturer id number 1100 0001= infineon technologies version number 15:8 data version number 0000 0010 = b21 data sheet 39 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.2 spi message #1 - control meth od and fault mask configuration sent values: control method and fault mask configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id cm0 cm1 cm2 cm3 cm4 cm5 cm6 cm7 0000001 1514131211109876543210 fm0 fm1 fm2 fm3 fm4 fm5 fm6 fm7 fmr fme diag_tmr unused msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0001 = control method and fault mask configuration cmx 23:16 data control mode for channel #x 0 = current cont rol (reset value) 1 = direct pwm fmx 15:8 data fault mask for channel #x 0 = faults don?t trigger fault pin (reset value) 1 = fault triggers fault pin fmr 7 data fault mask for reset_b pin 0 = reset_b=low doesn?t trigger fault pin (reset value) 1= reset_b=low does trigger fault pin fme 6 data fault mast for enable pin 0 = enable=low doesn?t trigger fault pin (reset value) 1 = enable=low does trigger fault pin diag_tmr 5:4 data diagnostic timer 00 = divide by 128, nfault = 10 ... 11 (reset value) 01 = divide by 192, nfault = 10 ... 11 10 = divide by 128, nfault = 2... 3 11 = divide by 256, nfault = 10 ... 11 TLE8242-2 functional description and electrical characteristics data sheet 40 rev. 1.0, 2010-02-09 response: control method and fault mask configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id cm0 cm1 cm2 cm3 cm4 cm5 cm6 cm7 0000001 1514131211109876543210 fm0 fm1 fm2 fm3 fm4 fm5 fm6 fm7 fmr fme diag_tmr 0 0 0 0 msb msb lsb field bits type description msg_id 30:24 addr message identifier 000 0001 = control method and fault mask configuration cmx 23:16 data control mode of channel #x 0 = current control (reset value) 1 = direct pwm fmx 15:8 data fault mask of channel #x 0 = faults don?t trigger fault pin (reset value) 1 = fault triggers fault pin fmr 7 data fault mask for reset_b pin 0 = reset_b=low doesn?t trig ger fault pin (reset value) 1 = reset_b=low does trigger fault pin fme 6 data fault mast for enable pin 0 = enable=low doesn?t trigger fault pin (reset value) 1 = enable=low does trigger fault pin diag_tmr 5:4 data diagnostic timer 00 = divide by 128, nfault = 10 ... 11 (reset value) 01 = divide by 192, nfault = 10 ... 11 10 = divide by 128, nfault = 2... 3 11 = divide by 256, nfault = 10 ... 11 data sheet 41 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.3 spi message #2 - diagnosti c configuration (channel 0-3) sent values: diagnostic configuration (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id sb0 sb_retry0 sb1 0000010msblsbmsb lsbmsblsb 1514131211109876543210 sb_retry1 sb2 sb_retry2 sb3 sb_retry3 msb lsb msb lsb msb lsb msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0010 = diagnostic configuration (channel 0-3) sbx 23:22, 17:16, 11:10, 5:4 data short to battery threshold 00 = 0.7v 01 = 0.9v 10 = 1.1v 11 = 1.3v (reset value) sb_retryx 21:18, 15:12, 9:6, 3:0 data short to battery retry time retry after 16* xxxx periods (reset value = 1111b or 240 pwm periods) response values: diagnostic configuration (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id sb0 sb_retry0 sb1 0000010msblsbmsb lsbmsblsb 1514131211109876543210 sb_retry1 sb2 sb_retry2 sb3 sb_retry3 msb lsb msb lsb msb lsb msb lsb msb lsb field bits type description msg_id 30:24 addr message identifier 000 0010 = diagnostic configuration (channel 0-3) TLE8242-2 functional description and electrical characteristics data sheet 42 rev. 1.0, 2010-02-09 equation: short to ba ttery retry period (1) sbx 23:22, 17:16, 11:10, 5:4 data short to battery threshold 00 = 0.7v 01 = 0.9v 10 = 1.1v 11 = 1.3v (reset value) sb_retryx 21:18, 15:12, 9:6, 3:0 data short to battery retry time retry after 16* xxxx periods (r eset value = 1111b or 240 pwm periods) field bits type description pwm x f sb_retry 16 period retry ? = data sheet 43 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.4 spi message #3 - diagnosti c configuration (channel 4-7) sent values: diagnostic configuration (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id sb4 sb_retry4 sb5 0000011msblsbmsb lsbmsblsb 1514131211109876543210 sb_retry5 sb6 sb_retry6 sb7 sb_retry7 msb lsb msb lsb msb lsb msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0011 = diagnostic configuration (channel 4-7) sbx 23:22, 17:16, 11:10, 5:4 data short to battery threshold 00 = 0.7v 01 = 0.9v 10 = 1.1v 11 = 1.3v (reset value) sb_retryx 21:18, 15:12, 9:6, 3:0 data short to battery retry time retry after 16 * xxxx periods (reset value = 1111b or 240 pwm periods) response values: diagnostic configuration (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id sb4 sb_retry4 sb5 0000011msblsbmsb lsbmsblsb 1514131211109876543210 sb_retry5 sb6 sb_retry6 sb7 sb_retry7 msb lsb msb lsb msb lsb msb lsb msb lsb field bits type description msg_id 30:24 addr message identifier 000 0011 = diagnostic configuration (channel 4-7) TLE8242-2 functional description and electrical characteristics data sheet 44 rev. 1.0, 2010-02-09 equation: short to ba ttery retry period (2) sbx 23:22, 17:16, 11:10, 5:4 data short to battery threshold 00 = 0.7v 01 = 0.9v 10 = 1.1v 11 = 1.3v (reset value) sb_retryx 21:18, 15:12, 9:6, 3:0 data short to battery retry time retry after 16* xxxx periods (r eset value = 1111b or 240 pwm periods) field bits type description pwm x f sb_retry 16 period retry ? = data sheet 45 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.5 spi message #4 - dia gnostic read (channel 0-3) sent values: diagnostic read (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused 0000100 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:24 addr message identifier 000 0100 = diagnostic read (channel 0-3) response values: diagnostic read (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0msg_idsg0 off- tst0 sb0 sb- tst0 ol- off0 ol- on0 sg1 off- tst1 0000100 1514131211109876543210 sb1 sb- tst1 ol- off1 ol- on1 sg2 off- tst2 sb2 sb- tst2 ol- off2 ol- on2 sg3 off- tst3 sb3 sb- tst3 ol- off3 ol- on3 field bits type description msg_id 30:24 addr message identifier 000 0100 = diagnostic read (channel 0-3) sgx 23, 17, 11, 5 data short to ground - fault (reset value = 0) off-tstx 22, 16, 10, 4 data short to ground & open ld (gate off) - tested (reset value = 0) sbx 21, 15, 9, 3 data short to battery - fault (reset value = 0) sb-tstx 20, 14, 8, 2 data short to battery - tested (reset value = 0) ol-offx 19, 13, 7, 1 data open load (gate off) - fault (reset value = 0) ol-onx 18, 12, 6, 0 data open load (gate on) - fault (reset value = 0) TLE8242-2 functional description and electrical characteristics data sheet 46 rev. 1.0, 2010-02-09 5.9.2.6 spi message #5 - dia gnostic read (channel 4-7) sent values: diagnostic read (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused 0000101 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write (interpreted as a read) msg_id 30:24 addr message identifier 000 0101 = diagnostic read (channel 4-7) response values: diagnostic read (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0msg_idsg4 off- tst4 sb4 sb- tst4 ol- off4 ol- on4 sg5 off- tst5 0000101 1514131211109876543210 sb5 sb- tst5 ol- off5 ol- on5 sg6 off- tst6 sb6 sb- tst6 ol- off6 ol- on6 sg7 off- tst7 sb7 sb- tst7 ol- off7 ol- on7 field bits type description msg_id 30:24 addr message identifier 000 0101 = diagnostic read (channel 4-7) sgx 23, 17, 11, 5 data short to ground - fault (reset value = 0) off-tstx 22, 16, 10, 4 data short to ground & open load (gate off) - tested (reset value = 0) sbx 21, 15, 9, 3 data short to battery - fault (reset value = 0) sb-tstx 20, 14, 8, 2 data short to battery - tested (reset value = 0) ol-offx 19, 13, 7, 1 data open load (gate off) - fault (reset value = 0) ol-onx 18, 12, 6, 0 data open load (gate on) - fault (reset value = 0) data sheet 47 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.7 spi message #6 - pwm offset (channel 0-3) sent values: pwm offset (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused offset0 0000110 msb 1514131211109876543210 offs et0 offset1 offset2 offset3 lsb msb lsb msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0110 = pwm offset (channel 0-3) offsetx 19:15, 14:10, 9:5, 4:0 data channelx pulse offset 1/32 of pwm period set by n and m values (reset value = 0) note: after exiting reset, a pulse on the phase_sync pin is needed to synchronize the channels response values: pwm offset (channels 0-3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id 0 0 0 0 offset0 0000110 msb 1514131211109876543210 offs et0 offset1 offset2 offset3 lsb msb lsb msb lsb msb lsb field bits type description msg_id 30:24 addr message identifier 000 0110 = pwm offset (channel 0-3) offsetx 19:15, 14:10, 9:5, 4:0 data channelx pulse offset 1/32 of period set by n value (reset value = 0) TLE8242-2 functional description and electrical characteristics data sheet 48 rev. 1.0, 2010-02-09 equation: phase sync offset (3) pwm x f * 32 offset offset synch phase = data sheet 49 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.8 spi message #7 - pwm offset (channel 4-7) sent values: pwm offset (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused offset4 0000111 msb 1514131211109876543210 offs et4 offset5 offset6 offset7 lsb msb lsb msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:24 addr message identifier 000 0111 = pwm offset (channel 4-7) offsetx 19:15, 14:10, 9:5, 4:0 data channelx pulse offset 1/32 of period set by n value (reset value = 0) note: after exiting reset, a pulse on the phase_sync pin is needed to synchronize the channels response values: pwm offset (channels 4-7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id 0 0 0 0 offset4 0000111 msb 1514131211109876543210 offs et4 offset5 offset6 offset7 lsb msb lsb msb lsb msb lsb field bits type description msg_id 30:24 addr message identifier 000 0111 = pwm offset (channel 4-7) offsetx 19:15, 14:10, 9:5, 4:0 data channelx pulse offset 1/32 of period set by n value (reset value = 0) TLE8242-2 functional description and electrical characteristics data sheet 50 rev. 1.0, 2010-02-09 equation: phase sync offset (4) pwm x f * 32 offset offset synch phase = data sheet 51 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.9 spi message #8 - main period set sent values: main period set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused sam 0001msb lsb 1514131211109876543210 divider m divider n msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0001 = main period set chan 26:24 addr channel number sam 16 data sample summation method 0 = use all values of samples (reset value) 1 = throw out first adc samples after an outx pin transition and use previous sample twice in the average calculation divider m 15:14 data divider m (number of a/d samples per pwm period) 00 = 32 (reset value) 01 = 64 10 = 128 11 = 512 (direct pwm) = 128 (current control) divider n 13:0 data divider n (number of main clk periods between a/d samples) (reset value = 271 h or 625 d ) t pwm = n*m*t clk & t adc = n*t clk TLE8242-2 functional description and electrical characteristics data sheet 52 rev. 1.0, 2010-02-09 equation: main period setting (5) response: main period set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 000000sam 0001msb lsb 1514131211109876543210 divider m divider n msb lsb msb lsb field bits type description msg_id 30:27 addr message identifier 0001 = main period set chan 26:24 addr channel number sam 16 data sample summation method 0 = use all values of samples (reset value) 1 = throw out first adc samples after an outx pin transition and use previous sample twice in the average calculation divider m 15:14 data divider m (number of a/d samples per pwm period) 00 = 32 (reset value) 01 = 64 10 = 128 11 = 512 (direct pwm) = 128 (current control) divider n 13:0 data divider n (number of main clk periods between a/d samples) (reset value = 271 h or 625 d ) t pwm = n*m*t clk & t adc = n*t clk seconds] [ f m n period pwm clk ? = data sheet 53 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics 5.9.2.10 spi message #9 - c ontrol variable set (k p and k i ) sent values: control variable set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan k p 0 0 1 0 msb lsb msb 1514131211109876543210 k p (cont) k i lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0010 =control variable set chan 26:24 addr channel number k p 23:12 control loop proportional coefficient (reset value = 0) k i 11:0 control loop integral coefficient (reset value = 0) response: control variable set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan k p 0 0 1 0 msb lsb msb 1514131211109876543210 k p (cont) k i lsb msb lsb field bits type description msg_id 30:27 addr message identifier 0010 =control variable set chan 26:24 addr channel number k p 23:12 data control loop proportional coefficient (reset value = 0) k i 11:0 data control loop integral coefficient (reset value = 0) TLE8242-2 functional description and electrical characteristics data sheet 54 rev. 1.0, 2010-02-09 5.9.2.11 spi message #10 - current and dither amplitude set sent values: current and dither amplitude set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan en unuse d dither step size 0011msb lsb msb 1514131211109876543210 dither step size (c ont) current setpoint lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0011 =current and dither amplitude set chan 26:24 addr channel number en 23 data operation during enable deactivation 0 = disable (reset value) 1 = remain in operation at last setpoint including dither dither step size 21:11 data dither step size (lsb?s value is 2 -2 of the current setpoint lsb) (reset value = 0) note: a value of 0 will disable the dither function current setpoint 10:0 data current set point (reset value = 0) data sheet 55 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics equation: dither amplitude setting (6) equation: average current setting (7) response: current and dither amplitude set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan en 0 dither step size 0011msb lsb msb 1514131211109876543210 dither step size (c ont) current setpoint lsb msb lsb field bits type description msg_id 30:27 addr message identifier 0011 =current and dither amplitude set chan 26:24 addr channel number en 23 data operation during enable deactivation 0 = disable (reset value) 1 = remain in operation at last setpoint including dither dither step size 21:11 data dither step size (lsb?s value is 2 -2 of the current setpoint lsb) (reset value = 0) note: a value of 0 will disable the dither function current setpoint 10:0 data current set point (reset value = 0) [] [ohm] rsense [mv] 320 2 steps dither stepsize dither 2 pp ma amplitude dither 13 ? ? ? = [] [ohm] rsense [mv] 320 2 setpoint current ma setting current average 11 ? = TLE8242-2 functional description and electrical characteristics data sheet 56 rev. 1.0, 2010-02-09 5.9.2.12 spi message #11 - dither period set sent values: dither period set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 0100msb lsb 1514131211109876543210 unused number of steps msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0100 =dither period set chan 26:24 addr channel number number of steps 4:0 data number of dither steps in 1/4 waveform (reset value = 0) note: a value of 0 will disable the dither function response: dither period set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 0000000 0100msb lsb 1514131211109876543210 00000000000 number of steps msb lsb field bits type description msg_id 30:27 addr message identifier 0100 =dither period set chan 26:24 addr channel number number of steps 4:0 data number of dither steps in 1/4 waveform (reset value = 0) note: a value of 0 will disable the dither function data sheet 57 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics equation: dither period setting (8) pwm f steps of number 4 period dither ? = TLE8242-2 functional description and electrical characteristics data sheet 58 rev. 1.0, 2010-02-09 5.9.2.13 spi message #12 - max / min current read peak sent values: max / min current read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 0101msb lsb 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0101 =max / min current read chan 26:24 addr channel number note: the channel selection for this message will also be the channel selected for the average current read over dither period. response: max / min current read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 valid max 0101msb lsb msb 1514131211109876543210 max (cont) min lsb msb lsb field bits type description msg_id 30:27 addr message identifier 0101 =current read chan 26:24 addr channel number valid 22 data valid reset when the register is read or when the channel number is changed (reset value = 0) set when a new data set is available. data sheet 59 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics equation: maximum dither current feedback (9) equation: minimum dither current feedback (10) note: when the selected channel is different than the previ ously selected channel (the last time this message was addressed), the new min and max data will be available after no more than two dither cycles. when the selected channel is the same as the previous ly selected channel, the new min and max data will be available in no more than one dither cycle. note: when m=512 in direct pwm mode, the following formul a applies. the application software must ensure that the register has not overflowed. equation: min/max dither current feedback m=512 (11) max 21:11 data the largest summation of ?m? a/d samples (within one pwm period) during the previous dither cycle. the 11 most significant bits are reported. note: return value will be 0 until the first dither cycle is completed - (reset value = 0) min 10:0 data the smallest summation of ?m? a/d samples (within one pwm period) during the previous dither cycle. the 11 most significant bits are reported. note: return value will be 2047until the first dither cycle is completed - (reset value = 2047) field bits type description [] [ohm] rsense [mv] 320 2 max ma feedback current max 11 ? = [] [ohm] rsense [mv] 320 2 min ma feedback current min 11 ? = [] [ohm] rsense [mv] 320 2 max or min ma feedback current max min / 13 ? = TLE8242-2 functional description and electrical characteristics data sheet 60 rev. 1.0, 2010-02-09 5.9.2.14 spi message #13 - average cu rrent read over dither period sent values: average dither current read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 0110msb lsb 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0110 =dither current read chan 26:24 addr channel number response: average dither current read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 0 0 valid average dither current 0110msb lsb msb 1514131211109876543210 average dither current (cont) lsb field bits type description msg_id 30:27 addr message identifier 0110 =dither current read chan 26:24 addr channel number note: the channel selection for this message will also be the channel selected for the max / min current read command. valid 20 data valid bit reset when register is read or when channel number is changed. set when new data is available. (reset value = 0) data sheet 61 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics equation: average dither current feedback with dither enabled (12) equation: average dither current feedback with dither disabled (13) note: when the selected channel is different than the previ ously selected channel (the last time this message was addressed), the new average dither curr ent data will be available after no mo re than two dither cycles. when the selected channel is the same as th e previously selected channel, the new average dither current data will be available in no more than one dither cycle. note: when m=512 in direct pwm mode, the following formul a applies. the application software must ensure that the register has not overflowed. equation: average dither current feedback m=512 with dither enabled (14) equation: average dither current feedback m=512 with dither disabled (15) average dither current 19:0 data 20 bit summation of the total current over a dither period. (reset value = 0) field bits type description [] [ohm] rsense [mv] 320 steps dither 2 current dither avg ma feedback current dither 15 ? ? = [] [ohm] rsense [mv] 320 2 current dither avg ma feedback current dither 13 ? = [] [ohm] rsense [mv] 320 steps dither 2 current dither avg ma feedback current dither 17 ? ? = [] [ohm] rsense [mv] 320 2 current dither avg ma feedback current dither 15 ? = TLE8242-2 functional description and electrical characteristics data sheet 62 rev. 1.0, 2010-02-09 5.9.2.15 spi message #14 - autozero trigger / read sent values: autozero trigger read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 0111msb lsb 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 0111 =autozero trigger / read chan 26:24 addr channel number response: autozero trigger read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 00000azonazoff 0111msb lsb 1514131211109876543210 azon value azoff value msb lsb msb lsb field bits type description msg_id 30:27 addr message identifier 0111 =autozero trigger / read chan 26:24 addr channel number azon 17 data autozero - gate on has occurred since last read 0 = not occurred (reset value) 1 = has occurred azoff 16 data autozero - gate off has occurred since last read 0 = not occurred (reset value) 1 = has occurred data sheet 63 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics when this register is written an auto-zero sequence is initiated for the selected channel, and the azon and azoff bits are reset. the azon and azoff bits are set after the autozero sequence has completed. when this register is read, the au to-zero sequence is not initiated, but the azon and azoff bits are reset. note: when a channel tran sitions from on to off, the auto zero sequence for that channe l must not be initiated until the recirculation cu rrent has fully decayed to 0 ma . otherwise, the calculated auto zero values will be incorrect resulting in inaccurate current regulation when a non-zero setpoint is programmed. equation: auto-zero value (16) az on value 15:8 data autozero value - gate on az off value 7:0 data autozero value - gate off field bits type description [] [ohm] rsense [mv] 320 2 az_value ma offset autozero 11 ? = TLE8242-2 functional description and electrical characteristics data sheet 64 rev. 1.0, 2010-02-09 5.9.2.16 spi message #15 - pwm duty cycle sent values: pwm duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused pwm duty cycle 1000msb lsb msb 1514131211109876543210 pwm duty cycle (cont) lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 1000 =pwm duty cycle chan 26:24 addr channel number pwm duty cycle 18:0 data pwm duty cycle this is used when control mode is set to ?direct pwm?. see the ?control method and fault mask configuration? message. if this message is written when the control m ode is set to ?current control? the pwm data will be stored but not used until the control mode is switched to ?direct pwm?. (reset value = 0) data sheet 65 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics note: the duty cycle of 100% can be achieved. although the above form ula may result in duty cycle values greater than 100%, the actual duty cycle is of course limited to 100%. equation: pwm duty cycle readout for constant current mode operation (17) equation: pwm duty cycle readout for direct pwm mode operation (18) note: the duty cycle of 100% can be achieved. although the above form ula may result in duty cycle values greater than 100%, the actual duty cycle is of course limited to 100%. response: pwm duty cycle 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 0 0 pwm duty cycle 1 0 0 0 msb lsb msb 1514131211109876543210 pwm duty cycle (cont) lsb field bits type description msg_id 30:27 addr message identifier 1000 =pwm duty cycle chan 26:24 addr channel number pwm duty cycle 20:0 data pwm duty cycle this will report the duty cycle bits in the register. if the channel is set to ?current control? the feedback will re present the valu e calculated by the pi controller. if the channel is set to ?direct pwm? the feedback will represent the value in the regi ster programmed by a spi write with bits 11 and 12 always read as 0. see the ?control method and fault mask configuration? message . (reset value = 0) [] 100% m n cycle duty pwm % cycle duty ? ? = [] 100% 32 n cycle duty pwm % cycle duty ? ? = TLE8242-2 functional description and electrical characteristics data sheet 66 rev. 1.0, 2010-02-09 5.9.2.17 spi message #16 - current profile detection setup 1 sent values: current profile detection setup 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan threshold 3 threshold 2 10 1001msb lsbmsb lsbmsb lsb 1514131211109876543210 threshold 1 count 3 count 2 count 1 msb lsb msb lsb msb lsb msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 1001 =current profile setup 1 chan 26:24 addr channel number threshold 3 23:20 data threshold 3 (zone 3) (reset value = 0) threshold 2 19:16 data threshold 2 (zone 2) (reset value = 0) threshold 1 15:12 data threshold 1 (zone 1) (reset value = 0) count 3 11:8 data count 3 (zone 3) (reset value = 0) count 2 7:4 data count 2 (zone 2 (reset value = 0) count 1 3:0 data count 1 (zone 1) (reset value = 0) data sheet 67 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics response: current profile detection setup 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan thresh old 3 threshold 2 1 0 0 1 msb lsb msb lsb msb lsb 1514131211109876543210 threshold 1 count 3 count 2 count 1 msb lsb msb lsb msb lsb msb lsb field bits type description msg_id 30:27 addr message identifier 1001 =current profile setup 1 chan 26:24 addr channel number threshold 3 23:20 data threshold 3 (zone 3) (reset value = 0) threshold 2 19:16 data threshold 2 (zone 2) (reset value = 0) threshold 1 15:12 data threshold 1 (zone 1) (reset value = 0) count 3 11:8 data count 3 (zone 3) (reset value = 0) count 2 7:4 data count 2 (zone 2) (reset value = 0) count 1 3:0 data count 1 (zone 1) (reset value = 0) TLE8242-2 functional description and electrical characteristics data sheet 68 rev. 1.0, 2010-02-09 5.9.2.18 spi message #17 - current profile detection setup 2 sent values: current profile detection setup 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 1010msb lsb 1514131211109876543210 unused time out unused zone 3 set msb lsb field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 1010 =current profile setup 2 chan 26:24 addr channel number time out 9:4 data current profile time out 1 lsb = 16 adc sample periods (reset value = 0) zone 3 set 1:0 data zone 3 a/d setup 00: addiff=a/d m - a/d m-1 01: addiff=a/d m - a/d m-2 10: addiff=a/d m - a/d m-3 11: addiff=a/d m - a/d m-4 response: current profile detection setup 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 0000000 1010msb lsb 1514131211109876543210 000000 time out 00zone3 set msb lsb field bits type description msg_id 30:27 addr message identifier 1010 =current profile setup 2 chan 26:24 addr channel number data sheet 69 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics time out 9:4 data current profile time out 1 lsb = 16 adc sample periods (reset value = 0) zone 3 set 1:0 data zone 3 a/d setup 00: addiff=a/d m - a/d m-1 01: addiff=a/d m - a/d m-2 10: addiff=a/d m - a/d m-3 11: addiff=a/d m - a/d m-4 field bits type description TLE8242-2 functional description and electrical characteristics data sheet 70 rev. 1.0, 2010-02-09 5.9.2.19 spi message #18 - current profile detection feedback sent values: current profile detection feedback 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id chan unused 1011msb lsb 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 1011 =current profile detection feedback chan 26:24 addr channel number response: current profile detection feedback 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id chan 0 0000000 1011msb lsb 1514131211109876543210 0000000000000 detect intrpt time- out pass field bits type description msg_id 30:27 addr message identifier 1011 =current profile detection feedback chan 26:24 addr channel number detection interrupted 2data detect interrupt bit (reset value = 0) reset when this register is read. set when the gate of the external fet is commanded off before the current profile detection sequence has completed. data sheet 71 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics time out 1 data current profile timeout (reset value = 0) reset when this register is read. set when the programmable time-out timer expires before the current profile detection sequence has completed. pass 0 data passed since last read (reset value = 0) reset when this register is read. set when the current profile detection sequence has completed before the programmed time-out timer expired and before the gate is turned off. table 7 interpretation of bits 2 to 0 detect interrupt bit current profile timeout passed since last read meaning 0 0 0 a current profile sequence has not completed since the last read of this register x x 1 at least one current profile sequence has completed successfully since the last read of this register x 1 x at least one time out failure has occurred since the last read of this register 1 x x at least one detect interrupt failure has occurred since the last read of this register. field bits type description TLE8242-2 functional description and electrical characteristics data sheet 72 rev. 1.0, 2010-02-09 5.9.2.20 spi message #19 - read generic flag bits sent values: read generic flag bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w msg_id unused 1111 1514131211109876543210 unused field bits type description r/w 31 read / write bit 0 = read 1 = write msg_id 30:27 addr message identifier 1111 = read generic flag bits response: read generic flag bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 msg_id 00000000000 1111 1514131211109876543210 000000000000ovpsen_lrb_l field bits type description msg_id 30:27 addr message identifier 1111 = read generic flag bits ov 3 data overvoltage has occurred since last read 0 = not occurred (reset value) 1 = has occurred ps 2 data phase synch has occurred since last read 0 = not occurred (reset value) 1 = has occurred en_l 1 data enable latch bit (reset value = 1) set to 0 when this register is read and enable pin is high set to 1 when the enable pin is low data sheet 73 rev. 1.0, 2010-02-09 TLE8242-2 functional description and electrical characteristics rb_l 0 data reset_b latch bit (reset value = 1) set to 0 when this register is read. set to 1 when the a high to low tr ansition occurs on the reset_b pin field bits type description TLE8242-2 application information data sheet 74 rev. 1.0, 2010-02-09 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 20 application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. 6.1 further application information ? please contact us to get the pin fmea ? for further information you may contact http://www.infineon.com/ channel 7 current control current control ?protection ? d iagnostic ?dither ? c urrent signature channel 6 current control current control ?protection ? d iagnostic ? d ither ? c urrent signature channel 5 current control current control ?protection ? d iagnostic ? d ither ? current signature channel 4 current control current control ?protection ? diagnostic ?dither ? current profile channel 3 current control current control ?protection ? d iagnostic ? d ither ? c urrent signature channel 2 current control current control ?protection ? d iagnostic ?dither ? current signature channel 1 current control current control ?protection ? d iagnostic ? d ither ? c urrent signature logic spi controller (example tc1767) v_signal cs_b sck si so gnda1 power supply (example tle7368) v5d bat channel 0 current control current control ?protection ? diagnostic ?dither ? current profile out0 neg0 pos0 spd15n06s2l-64 0.2 ohm solenoi d battery uc i/o supply +3.3v or +5.0v +5v switched battery out + gnda2 gnda3 gndsd gndd v5a1 +5v analog v5a2 v5a3 battery input one capacitor for all v5a pins may be sufficient the gnda pins must be connected to a low impedance ground plane directly at the pin phase_sync reset_b enable clk fault test v_signal gndsa low z paths are required between posx, negx and the sense resistor tle 8242 sci3 sco2 sco3 amux data sheet 75 rev. 1.0, 2010-02-09 TLE8242-2 package outlines 7 package outlines figure 21 pg-lqfp-64 green product (rohs-compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020). you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm TLE8242-2 package outlines data sheet 76 rev. 1.0, 2010-02-09 data sheet 77 rev. 1.0, 2010-02-09 TLE8242-2 revision history 8 revision history revision date changes 1.0 2009-02-24 page 6, figures 1 and 2 : improved figure quality page 7, improved description of sam bit functionality pages 24 to 26, figures 10, 11, 13, and 14: improved figure quality pages 51 and 52: improved description of sam bit functionality pages 72: corrected the name of the register in the msg_id descriptions page 74, figure 21 : updated the package outline drawing 1.0 2009-12-09 changes from tle8242l rev 1.0 datasheet 1.0 2009-12-09 section 1.3.2, equation for duty-cyc le: revised equation to include the m variable. m is the # of adc samples per pwm period. revised equation for calculating the duration of the autozero procedure 1.0 2009-12-09 section 5.3, added new filter times to table 2 1.0 2009-12-09 section 5.3.2, elec trical table, parameters 5.3.12 through 5.3.15 revised with new filter times 1.0 2009-12-09 section 5.9.2.1, revised ic version number 1.0 2009-12-09 section 5.9.2.2, added new filter times. 1.0 2009-12-09 section 5.9.2.14, added equations for current feedback value when dither is disabled 1.0 2009-12-09 section 5.9.2.14, added equation for autozero offset value 1.0 2009-12-09 section 5.9.2.7 and 5.9.2.8, added note that a puls e is needed on the phase_sync pin to synchronize the channels after exiting the reset state. 1.0 2009-12-09 section 5.7.1, added maximum valu e of analog to digital converter sample rate 1.0 2009-12-09 section 5.2, added note that a pulse is needed on the phase_sync pin in order to synchronize the pwm periods of the channels after exiting the reset state edition 2010-02-09 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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